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1 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram 2mb zbt ? sram features ? high frequency and 100 percent bus utilization fast cycle times: 7.5ns and 10ns single +3.3v 5% power supply advanced control logic for minimum control signal interface individual byte write controls may be tied low single r/w# (read/write) control pin cke# pin to enable clock and suspend operations three chip enables for simple depth expansion clock-controlled and registered addresses, data i/os and control signals internally self-timed, fully coherent write internally self-timed, registered outputs eliminate the need to control oe# snooze mode for reduced-power standby common data inputs and data outputs linear or interleaved burst modes burst feature (optional) pin/function compatibility with 4mb, 8mb, and 16mb zbt sram 100-pin tqfp package 165-pin fbga package automatic power-down options marking timing (access/cycle/mhz) 4.2ns/7.5ns/133 mhz -7.5 5ns/10ns/100 mhz -10 configurations 128k x 18 mt55l128l18p1 64k x 32 MT55L64L32P1 64k x 36 mt55l64l36p1 package 100-pin tqfp t 165-pin fbga f temperature commercial (0c to +70c) none part number example: mt55l128l18p1t-10* * a part marking guide for the fbga devices can be found on micron?s web site? http://www.micron.com/support/index.html . mt55l128l18p1, MT55L64L32P1, mt55l64l36p1 3.3v v dd , 3.3v i/o **jedec-standard ms-026 bha (lqfp). 100-pin tqfp** general description the micron ? zero bus turnaround ? (zbt ? ) sram family employs high-speed, low-power cmos designs using an advanced cmos process. the mt55l128l18p1 and mt55l64l32/36p1 srams integrate a 128k x 18, 64k x 32, or 64k x 36 sram core with advanced synchronous peripheral circuitry and a 2-bit burst counter. these srams are optimized for 100 percent bus utilization, eliminating turnaround cycles for read to write, or write to read, transitions. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (clk). the synchronous inputs include all addresses, all data inputs, chip enable (ce#), two additional chip enables for easy depth expansion (ce2, ce2#), cycle start input 165-pin fbga (preliminary package data)
2 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram note: functional block diagrams illustrate simplified device operation. see truth tables, pin descriptions and timing diagrams for detailed information. functional block diagram 128k x 18 k mode 17 bwa# bwb# r/w# ce# ce2 ce2# oe# read logic dqpa dqpb d a t a s t e e r i n g o u t p u t b u f f e r s 128k x 9 x 2 memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic 17 17 15 17 burst logic sa0' sa1' d1 d0 q1 q0 sa0 sa1 k 17 adv/ld# adv/ld# e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e clk cke# write drivers sa0, sa1, sa 18 18 18 18 k mode 16 bwa# bwb# bwc# bwd# r/w# ce# ce2 ce2# oe# read logic dqpa dqpb dqpc dqpd d a t a s t e e r i n g o u t p u t b u f f e r s 64k x 8 x 4 (x32) 64k x 9 x 4 (x36) memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic 16 16 14 16 burst logic sa0' sa1' d1 d0 q1 q0 sa0 sa1 k 16 adv/ld# adv/ld# e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e clk cke# write drivers sa0, sa1, sa 36 36 36 36 functional block diagram 64k x 32/36
3 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram cycle. for example, if a write cycle begins in clock cycle one, the address is present on rising edge one. byte writes need to be asserted on the same cycle as the address. the data associated with the address is required two cycles later, or on the rising edge of clock cycle three. address and write control are registered on-chip to simplify write cycles. this allows self-timed write cycles. individual byte enables allow individual bytes to be written. during a byte write cycle, bwa# controls dqa pins; bwb# controls dqb pins; bwc# controls dqc pins; and bwd# controls dqd pins. cycle types can only be defined when an address is loaded, i.e., when adv/ld# is low. parity/ecc bits are only available on the x18 and x36 versions. micron?s 2mb zbt srams operate from a +3.3v v dd power supply, and all inputs and outputs are lvttl- compatible. the device is ideally suited for systems requiring high bandwidth and zero bus turnaround delays. please refer to micron?s web site ( www.micronsemi.com/datasheets/zbtds.html ) for the latest data sheet. (adv/ld#), synchronous clock enable (cke#), byte write enables (bwa#, bwb#, bwc# and bwd#) and read/write (r/w#). asynchronous inputs include the output enable (oe#, which may be tied low for control signal mini- mization), clock (clk) and snooze enable (zz, which may be tied low if unused). there is also a burst mode pin (mode) that selects between interleaved and linear burst modes. mode may be tied high, low or left unconnected if burst is unused. the data-out (q), enabled by oe#, is registered by the rising edge of clk. write cycles can be from one to four bytes wide as controlled by the write control inputs. all read, write, and deselect cycles are initi- ated by the adv/ld# input. subsequent burst ad- dresses can be internally generated as controlled by the burst advance pin (adv/ld#). use of burst mode is optional. it is allowable to give an address for each individual read and write cycle. burst cycles wrap around after the fourth access from a base address. to allow for continuous, 100 percent use of the data bus, the pipelined zbt sram uses a late late write general description (continued) pin # x18 x32 x36 51 nc nc dqa 52 nc dqa dqa 53 nc dqa dqa 54 v dd q 55 v ss 56 nc dqa dqa 57 nc dqa dqa 58 dqa 59 dqa 60 v ss 61 v dd q 62 dqa 63 dqa 64 zz 65 v dd 66 v dd 67 v ss 68 dqa dqb dqb 69 dqa dqb dqb 70 v dd q 71 v ss 72 dqa dqb dqb 73 dqa dqb dqb 74 dqpa dqb dqb 75 nc dqb dqb pin # x18 x32 x36 76 v ss 77 v dd q 78 nc dqb dqb 79 nc dqb dqb 80 sa nc dqpb 81 sa 82 sa 83 nf* 84 nf* 85 adv/ld# 86 oe# (g#) 87 cke# 88 r/w# 89 clk 90 v ss 91 v dd 92 ce2# 93 bwa# 94 bwb# 95 nc bwc# bwc# 96 nc bwd# bwd# 97 ce2 98 ce# 99 sa 100 sa pin # x18 x32 x36 pin assignment table pin # x18 x32 x36 1ncnc dqpc 2nc dqpc dqpc 3nc dqc dqc 4v dd q 5v ss 6nc dqc dqc 7nc dqc dqc 8 dqb dqc dqc 9 dqb dqc dqc 10 v ss 11 v dd q 12 dqb dqc dqc 13 dqb dqc dqc 14 v dd 15 v dd 16 v dd 17 v ss 18 dqb dqd dqd 19 dqb dqd dqd 20 v dd q 21 v ss 22 dqb dqd dqd 23 dqb dqd dqd 24 dqpb dqd dqd 25 nc dqd dqd 26 v ss 27 v dd q 28 nc dqd dqd 29 nc dqd dqd 30 nc nc dqpd 31 mode (lbo#) 32 sa 33 sa 34 sa 35 sa 36 sa1 37 sa0 38 dnu 39 dnu 40 v ss 41 v dd 42 dnu 43 dnu 44 sa 45 sa 46 sa 47 sa 48 sa 49 sa 50 nc/ sa * * pins 50, 83, and 84 are reserved for address expansion.
4 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram pin assignment (top view) 100-pin tqfp sa sa nf** nf** adv/ld# oe# (g#) cke# r/w# clk v ss v dd ce2# bwa# bwb# nc nc ce2 ce# sa sa 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 sa nc nc v dd q v ss nc dqpa dqa dqa v ss v dd q dqa dqa v ss v dd v dd zz dqa dqa v dd q v ss dqa dqa nc nc v ss v dd q nc nc nc nc/ sa ** sa sa sa sa sa sa dnu dnu v dd v ss dnu dnu sa0 sa1 sa sa sa sa mode (lbo#) nc nc nc v dd q v ss nc nc dqb dqb v ss v dd q dqb dqb v dd v dd v dd v ss dqb dqb v dd q v ss dqb dqb dqpb nc v ss v dd q nc nc nc x18 sa sa nf** nf** adv/ld# oe# (g#) cke# r/w# clk v ss v dd ce2# bwa# bwb# bwc# bwd# ce2 ce# sa sa 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 nc/ dqpb * dqb dqb v dd q v ss dqb dqb dqb dqb v ss v dd q dqb dqb v ss v dd v dd zz dqa dqa v dd q v ss dqa dqa dqa dqa v ss v dd q dqa dqa nc/ dqpa * nc/ sa ** sa sa sa sa sa sa dnu dnu v dd v ss dnu dnu sa0 sa1 sa sa sa sa mode (lbo#) nc/ dqpc * dqpc dqc v dd q v ss dqc dqc dqc dqc v ss v dd q dqc dqc v dd v dd v dd v ss dqd dqd v dd q v ss dqd dqd dqd dqd v ss v dd q dqd dqd nc/ dqpd * x32/x36 * nc for x32 version, dqpx for x36 version. ** pins 50, 83, and 84 are reserved for address expansion.
5 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram pin descriptions tqfp (x18) tqfp (x32/x36) symbol type description 37 37 sa0 input synchronous address inputs: these inputs are registered 36 36 sa1 and must meet the setup and hold times around the rising 32-35, 44-49, 32-35, 44-49, sa edge of clk. pins 50, 83, and 84 are reserved as address 80-82, 99, 100 81, 82, 99, 100 bits for the higher-density 4mb, 8mb, and 16mb zbt srams, respectively. sa0 and sa1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. 93 93 bwa# input synchronous byte write enables: these active low inputs 94 94 bwb# allow individual bytes to be written when a write cycle is ? 95 bwc# active and must meet the setup and hold times around ? 96 bwd# the rising edge of clk. bws are associated with addresses and apply to subsequent data. byte writes need to be asserted on the same cycle as the address. bwa# controls dqa pins; bwb# controls dqb pins; bwc# controls dqc pins; bwd# controls dqd pins. 89 89 clk input clock: this signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock ? s rising edge. 98 98 ce# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded (adv/ld# low). 92 92 ce2# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded (adv/ld# low). this input can be used for memory depth expansion. 97 97 ce2 input synchronous chip enable: this active high input is used to enable the device and is sampled only when a new external address is loaded (adv/ld# low). this input can be used for memory depth expansion. 86 86 oe# input output enable: this active low, asynchronous input (g#) enables the data i/o output drivers. g# is the jedec- standard term for oe#. 85 85 adv/ld# input synchronous address advance/load: when high, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. when adv/ld# is high, r/w# is ignored. a low on adv/ld# clocks a new address at the clk rising edge. 87 87 cke# input synchronous clock enable: this active low input permits clk to propagate throughout the device. when cke# is high, the device ignores the clk input and effectively internally extends the previous clk cycle. this input must meet setup and hold times around the rising edge of clk. 64 64 zz input snooze enable: this active high, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. when zz is active, all other inputs are ignored.
6 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram pin descriptions (continued) tqfp (x18) tqfp (x32/x36) symbol type description 88 88 r/w# input read/write: this input determines the cycle type when adv/ld# is low and is the only means for determining reads and writes. read cycles may not be converted into writes (and vice versa) other than by loading a new address. a low on this pin permits byte write opera- tions and must meet the setup and hold times around the rising edge of clk. full bus-width writes occur if all byte write enables are low. 38, 39, 42, 43 38, 39, 42, 43 dnu ? do not use: these signals may either be unconnected or wired to gnd to minimize thermal impedance. (a) 58, 59, 62, 63, (a) 52, 53, dqa input/ sram data i/os: byte ? a ? is dqa pins; byte ? b ? is dqb 68, 69, 72, 73 56-59, 62, 63 output pins; byte ? c ? is dqc pins; byte ? d ? is dqd pins. input data (b) 8, 9, 12, 13, (b) 68, 69, dqb must meet setup and hold times around the rising edge of 18, 19, 22, 23 72-75, 78, 79 clk. (c) 2, 3, 6-9, dqc 12, 13 (d) 18, 19, dqd 22-25, 28, 29 74 51 nc/ dqpa nc/ no connect/data bits: on the x32 version, these pins are 24 80 nc/ dqpb i/o no connect (nc) and can be left floating or connected to 1 nc/ dqpc gnd to minimize thermal impedance. on the x36 version, 30 nc/ dqpd these bits are dqs. 1-3, 6, 7, 25, n/a nc nc no connect: these pins can be left floating or connected 28-30, 51-53, to gnd to minimize thermal impedance. 56, 57, 75, 78, 79, 95, 96 31 31 mode input mode: this input selects the burst sequence. a low on (lbo#) this pin selects linear burst. nc or high on this pin selects interleaved burst. do not alter input state while device is operating. lbo# is the jedec-standard term for mode. 50 50 nc/ sa nc no connect: nc pin 50 is reserved as an address bit for the higher-density 4mb zbt sram. this pin can be left floating or connected to gnd to minimize thermal impedance. 83, 84 83, 84 nf ? no function: these pins are internally connected to the die and will have the capacitance of an input pin. it is allowable to leave these pins unconnected or driven by signals. pins 83 and 84 are reserved as address bits for the 8mb and 16mb zbt srams. 14-16, 41, 65, 14-16, 41, 65, v dd supply power supply: see dc electrical characteristics and 66, 91 66, 91 operating conditions for range. 4, 11, 20, 27, 4, 11, 20, 27, v dd q supply isolated output buffer supply: see dc electrical 54, 61, 70, 77 54, 61, 70, 77 characteristics and operating conditions for range. 5, 10, 17, 21, 26, 5, 10, 17, 21, v ss supply ground: gnd. 40, 55, 60, 67, 71, 26, 40, 55, 60, 76, 90 67, 71, 76, 90
7 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram pin layout (top view) 165-pin fbga a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 2 ce# ce2 v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc dqb dqb dqb dqb v dd nc nc nc nc nc nc nc nc nc nc nc nc nc nc v dd dqb dqb dqb dqb dqpb nc mode (lbo#) bwb# nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa nc bwa# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss nc dnu dnu ce2# clk v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss nc sa1 sa0 cke# r/w# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v dd dnu dnu adv/ld# oe# (g#) v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa nc nc v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc nc nc nc nc nc dqa dqa dqa dqa nc sa sa sa nc dqpa dqa dqa dqa dqa zz nc nc nc nc nc nc nc top view 3456789 10 11 1 a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 2 ce# ce2 v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc dqc dqc dqc dqc v dd dqd dqd dqd dqd nc nc nc nc nc nc/ dqpc dqc dqc dqc dqc v dd dqd dqd dqd dqd nc/ dqpd nc mode (lbo#) bwc# bwd# v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa bwb# bwa# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss nc dnu dnu ce2# clk v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss nc sa1 sa0 cke# r/w# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v dd dnu dnu adv/ld# oe# (g#) v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa nc nc v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc dqb dqb dqb dqb nc dqa dqa dqa dqa nc sa sa nc nc nc/ dqpb dqb dqb dqb dqb zz dqa dqa dqa dqa nc/ dqpa nc nc top view 3456789 10 11 1 x18 x32/x36 *no connect (nc) is used on the x32 version. parity (dqpx) is used on the x36 version.
8 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram fbga pin descriptions x18 x32/x36 symbol type description 6r 6r sa0 input synchronous address inputs: these inputs are registered and must 6p 6p sa1 meet the setup and hold times around the rising edge of clk. 2a, 2b, 3p, 2a, 2b, 3p, sa 3r, 4p, 4r, 3r, 4p, 4r, 8p, 8r, 9p, 8p, 8r, 9p, 9r, 10a, 10b 9r, 10a, 10b 10p, 10r, 11a 10p, 10r 5b 5b bwa# input synchronous byte write enables: these active low inputs allow 4a 5a bwb# individual bytes to be written and must meet the setup and hold ? 4a bwc# times around the rising edge of clk. a byte write enable is low ? 4b bwd# for a write cycle and high for a read cycle. for the x18 version, bwa# controls dqas and dqpa; bwb# controls dqbs and dqpb. for the x32 and x36 versions, bwa# controls dqas and dqpa; bwb# controls dqbs and dqpb; bwc# controls dqcs and dqpc; bwd# controls dqds and dqpd. parity is only available on the x18 and x36 versions. 6b 6b clk input clock: this signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock ? s rising edge. 3a 3a ce# input synchronous chip enable: this active low input is used to enable the device. ce# is sampled only when a new external address is loaded. 6a 6a ce2# i nput synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded. 7a 7a cke# input synchronous clock enable: this active low input permits clk to propagate throughout the device. when cke# is high, the device ignores the clk input and effectively internally extends the previous clk cycle. this input must meet setup and hold times around the rising edge of clk. 11h 11h zz input snooze enable: this active high, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. when zz is active, all other inputs are ignored. 7b 7b r/w# input read/write: this input determines the cycle type when adv/ld# is low and is the only means for determining reads and writes. read cycles may not be converted into writes (and vice versa) other than by loading a new address. a low on this pin permits byte write operations and must meet the setup and hold times around the rising edge of clk. full bus-width writes occur if all byte write enables are low. 3b 3b ce2 input synchronous chip enable: this active high input is used to enable the device and is sampled only when a new external address is loaded. (continued on next page)
9 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram (continued on next page) fbga pin descriptions (continued) x18 x32/x36 symbol type description 8b 8b oe#(g#) i nput output enable: this active low, asynchronous input enables the data i/o output drivers. 8a 8a adv/ld# input synchronous address advance/load: when high, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. when adv/ld# is high, r/w# is ignored. a low on adv/ld# clocks a new address at the clk rising edge. 1r 1r mode input mode: this input selects the burst sequence. a low on this (lb0#) input selects ? linear burst. ? nc or high on this input selects ? interleaved burst. ? do not alter input state while device is operating. (a) 10j, 10k, (a) 10j, 10k, dqa input/ sram data i/os: for the x18 version, byte ? a ? is associated dqas; 10l, 10m, 11d, 10l, 10m, 11j, output byte ? b ? is associated with dqbs. for the x32 and x36 versions, 11e, 11f, 11g 11k, 11l, 11m byte ? a ? is associated with dqas; byte ? b ? is associated with dqbs; (b) 1j, 1k, (b) 10d, 10e, dqb byte ? c ? is associated with dqcs; byte ? d ? is associated with dqds. 1l, 1m, 2d, 10f, 10g, 11d, input data must meet setup and hold times around the rising edge 2e, 2f, 2g 11e, 11f, 11g of clk. (c) 1d, 1e, dqc 1f, 1g, 2d, 2e, 2f, 2g (d) 1j, 1k, 1l, dqd 1m, 2j, 2k, 2l, 2m 11c 11n nc/ dqpa nc/ no connect/parity data i/os: on the x32 version, these are no 1n 11c nc/ dqpb i/o connect (nc). on the x18 version, byte ? a ? parity is dqpa; byte ? b ? ? 1c nc/ dqpc parity is dqpb. on the x36 version, byte ? a ? parity is dqpa; byte ? 1n nc/ dqpd ? b ? parity is dqpb; byte ? c ? parity is dqpc; byte ? d ? parity is dqpd. 1h, 2h, 4d, 1h, 2h, 4d, v dd supply power supply: see dc electrical characteristics and operating 4e, 4f, 4g, 4e, 4f, 4g, conditions for range. 4h, 4j, 4k, 4h, 4j, 4k, 4l, 4m, 7n, 4l, 4m, 7n, 8d, 8e, 8f, 8d, 8e, 8f, 8g, 8h, 8j, 8g, 8h, 8j, 8k, 8l, 8m 8k, 8l, 8m 3c, 3d, 3e, 3c, 3d, 3e, v dd q supply isolated output buffer supply: see dc electrical characteristics 3f, 3g, 3j, 3f, 3g, 3j, and operating conditions for range. 3k, 3l, 3m, 3k, 3l, 3m, 3n, 9c, 9d, 3n, 9c, 9d, 9e, 9f, 9g, 9e, 9f, 9g, 9j, 9k, 9l, 9j, 9k, 9l, 9m, 9n 9m, 9n
10 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram fbga pin descriptions (continued) x18 x32/x36 symbol type description 4c, 4n, 5c, 4c, 4n, 5c, v ss supply ground: gnd. 5d, 5e 5f, 5d, 5e 5f, 5g, 5h, 5j, 5g, 5h, 5j, 5k, 5l, 5m, 5k, 5l, 5m, 6c, 6d, 6e, 6f, 6c, 6d, 6e, 6f, 6g, 6h, 6j, 6g, 6h, 6j, 6k, 6l, 6m, 6k, 6l, 6m, 7c, 7d, 7e, 7c, 7d, 7e, 7f, 7g, 7h, 7f, 7g, 7h, 7j, 7k, 7l, 7j, 7k, 7l, 7m, 8c, 8n 7m, 8c, 8n 5p, 5r, 7p, 7r 5p, 5r, 7p, 7r dnu ? do not use: these signals may either be unconnected or wired to gnd to improve package heat dissipation. 1a, 1b, 1c, 1a, 1b, 1p, nc ? no connect: these signals are not internally connected and 1d, 1e, 1f, 2c, 2n, 2p, may be connected to ground to improve package heat 1g, 1p, 2c, 2r, 3h, 5n, dissipation. 2j, 2k, 2l, 6n, 9a, 9b, 2m, 2n, 2p, 9h, 10c, 2r, 3h, 4b, 10h, 10n, 5a, 5n, 6n, 11a, 11b, 9a, 9b, 9h, 11p, 11r 10c, 10d, 10e, 10f, 10g, 10h, 10n, 11b, 11j, 11k, 11l, 11m, 11n, 11p, 11r
11 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram function r/w# bwa# bwb# bwc# bwd# read h x x x x write byte ? a ? llhhh write byte ? b ? lhlhh write byte ? c ? lhhlh write byte ? d ? l hhhl write all bytes lllll write abort/nop l h h h h interleaved burst address table (mode = nc or high) first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x00 x...x11 x...x10 x...x10 x...x11 x...x00 x...x01 x...x11 x...x10 x...x01 x...x00 linear burst address table (mode = low) first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x10 x...x11 x...x00 x...x10 x...x11 x...x00 x...x01 x...x11 x...x00 x...x01 x...x10 partial truth table for read/write commands (x32/x36) note: using r/w# and byte write(s), any one or more bytes may be written. function r/w# bwa# bwb# read h x x write byte ? a ? llh write byte ? b ? lhl write all bytes l l l write abort/nop l h h partial truth table for read/write commands (x18) note: using r/w# and byte write(s), any one or more bytes may be written.
12 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram state diagram for zbt sram note: 1. a stall or ignore clock edge cycle is not shown in the above diagram. this is because cke# high only blocks the clock (clk) input and does not change the state of the device. 2. states change on the rising edge of the clock (clk). deselect begin read burst read begin write ds ds ds burst write read ds write write burst read write read burst burst read burst ds write key: command ds read write burst operation deselect new read new write burst read, burst write or continue deselect burst read write
13 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram truth table (notes 5-10) operation address ce# ce2# ce2 zz adv/ r/w# bwx oe# cke# clk dq notes used ld# deselect cycle none h x x l l x x x l l ? h high-z deselect cycle none x h x l l x x x l l ? h high-z deselect cycle none x x l l l x x x l l ? h high-z continue deselect cycle none x x x l h x x x l l ? h high-z 1 read cycle external l l h l l h x l l l ? hq (begin burst) read cycle next x x x l h x x l l l ? h q 1, 11 (continue burst) nop/dummy read external l l h l l h x h l l ? h high-z 2 (begin burst) dummy read next x x x l h x x h l l ? h high-z 1, 2, (continue burst) 11 write cycle external l l h l l l l x l l ? hd 3 (begin burst) write cycle next x x x l h x l x l l ? h d 1, 3, (continue burst) 11 nop/write abort none l l h l l l h x l l ? h high-z 2, 3 (begin burst) write abort next x x x l h x h x l l ? h high-z 1, 2, (continue burst) 3, 11 ignore clock edge current x x x l x x x x h l ? h ? 4 (stall) snooze mode none x x x h x x x x x x high-z note: 1. continue burst cycles, whether read or write, use the same control inputs. the type of cycle performed (read or write) is chosen in the initial begin burst cycle. a continue deselect cycle can only be entered if a deselect cycle is executed first. 2. dummy read and write abort cycles can be considered nops because the device performs no external operation. a write abort means a write command is given, but no operation is performed. 3. oe# may be wired low to minimize the number of control signals to the sram. the device will automatically turn off the output drivers during a write cycle. oe# may be used when the bus turn-on and turn-off times do not meet an application ? s requirements. 4. if an ignore clock edge command occurs during a read operation, the dq bus will remain active (low-z). if it occurs during a write cycle, the bus will remain in high-z. no write operations will be performed during the ignore clock edge cycle. 5. x means ? don ? t care. ? h means logic high. l means logic low. bwx = h means all byte write signals (bwa#, bwb#, bwc# and bwd#) are high. bwx = l means one or more byte write signals are low. 6. bwa# enables writes to byte ? a ? (dqa pins); bwb# enables writes to byte ? b ? (dqb pins); bwc# enables writes to byte ? c ? (dqc pins); bwd# enables writes to byte ? d ? (dqd pins). 7. all inputs except oe# and zz must meet setup and hold times around the rising edge (low to high) of clk. 8. wait states are inserted by setting cke# high. 9. this device contains circuitry that will ensure that the outputs will be in high-z during power-up. 10. the device incorporates a 2-bit burst counter. address wraps to the initial address every fourth burst cycle. 11. the address counter is incremented for all continue burst cycles.
14 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram absolute maximum ratings* voltage on v dd supply relative to v ss ............................... -0.5v to +4.6v voltage on v dd q supply relative to v ss ................................... -0.5v to v dd v in ........................................... -0.5v to v dd q + 0.5v storage temperature (plastic) ............ -55c to +150c junction temperature** ................................... +150c short circuit output current ........................... 100ma *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. **junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. see micron technical note tn-05-14 for more information. dc electrical characteristics and operating conditions (0 c t a +70 c; v dd , v dd q = +3.3v 0.165v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage v ih 2.0 v dd + 0.3 v 1, 2 input high (logic 1) voltage dq pins v ih 2.0 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.8 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 a 3 output leakage current output(s) disabled, il o -1.0 1.0 a 0v v in v dd output high voltage i oh = -4.0ma v oh 2.4 ? v 1, 4 output low voltage i ol = 8.0ma v ol ? 0.4 v 1, 4 supply voltage v dd 3.135 3.465 v 1 isolated output buffer supply v dd q 3.135 v dd v 1, 5 note: 1. all voltages referenced to v ss (gnd). 2. overshoot: v ih +4.6v for t t khkh/2 for i 20ma undershoot: v il -0.7v for t t khkh/2 for i 20ma power-up: v ih +3.465v and v dd 3.135v for t 200ms 3. mode pin has an internal pull-up, and input leakage = 10a. 4. the load used for v oh , v ol testing is shown in figure 2. ac load current is higher than the shown dc values. ac i/o curves are available upon request. 5. v dd q should never exceed v dd . v dd and v dd q can be externally wired together to the same power supply. 6. this parameter is sampled. 7. preliminary package data. tqfp capacitance description conditions symbol typ max units notes control input capacitance t a = 25 c; f = 1 mhz c i 2.7 3.5 pf 6 input/output capacitance (dq) v dd = 3.3v c o 45pf6 address capacitance c a 2.5 3.5 pf 6 clock capacitance c ck 2.5 3.5 pf 6 fbga capacitance description conditions symbol typ max units notes address/control input capacitance c i 2.5 3.5 p f 6, 7 output capacitance (q) t a = 25 c; f = 1 mhz c o 4 5 p f 6, 7 clock capacitance c ck 2.5 3.5 p f 6, 7
15 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram i dd operating conditions and maximum limits (0 c t a +70 c; v dd , v dd q = +3.3v 0.165v unless otherwise noted) description conditions symbol typ -7.5 -10 units notes power supply device selected; all inputs v il or v ih ; current: cycle time t kc (min); i dd 100 280 225 ma 1, 2, 3 operating v dd = max; outputs open power supply device selected; v dd = max; current: idle cke# v ih ;i dd 1 10 25 20 ma 1, 2, 3 all inputs v ss + 0.2 or v dd - 0.2; cycle time t kc (min) cmos standby device deselected; v dd = max; all inputs v ss + 0.2 or v dd - 0.2; i sb 2 0.5 10 10 ma 2, 3 all inputs static; clk frequency = 0 ttl standby device deselected; v dd = max; all inputs v il or v ih ;i sb 3 7 25 25 ma 2, 3 all inputs static; clk frequency = 0 clock running device deselected; v dd = max; all inputs v ss + 0.2 or v dd - 0.2; i sb 4 30 70 65 ma 2, 3 cycle time t kc (min) snooze mode zz v ih i sb 2 z 0.5 10 10 ma 3 note: 1. i dd is specified with no output current and increases with faster cycle times. i dd q increases with faster cycle times and greater output loading. 2. ? device deselected ? means device is in a deselected cycle as defined in the truth table. ? device selected ? means device is active (not in deselected mode). 3. typical values are measured at 3.3v, 25 c, and 10ns cycle time. 4. this parameter is sampled. 5. preliminary package data. tqfp thermal resistance description conditions symbol typ units notes thermal resistance test conditions follow standard test methods q ja 40 c/w 4 (junction to ambient) and procedures for measuring thermal thermal resistance impedance, per eia/jesd51. q jc 8 c/w 4 (junction to top of case) max fbga thermal resistance description conditions symbol typ units notes junction to ambient test conditions follow standard test methods q ja 40 c/w 4, 5 (airflow of 1m/s) and procedures for measuring thermal junction to case (top) impedance, per eia/jesd51. q jc 9 c/w 4, 5 junction to pins q jb 17 c/w 4, 5 (bottom)
16 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram note: 1. measured as high above v ih and low below v il . 2. refer to technical note tn-55-01, ? designing with zbt srams, ? for a more thorough discussion on these parameters. 3. this parameter is sampled. 4. output loading is specified with c l = 5pf as shown in figure 2. 5. transition is measured 200mv from steady state voltage. 6. oe# can be considered a ? don ? t care ? during writes; however, controlling oe# can help fine-tune a system for turnaround timing. 7. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk when they are being registered into the device. all other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (clk) when the chip is enabled. chip enable must be valid at each rising edge of clk when adv/ld# is low to remain enabled. 8. test conditions as specified with the output loading shown in figure 1 unless otherwise noted. 9. a write cycle is defined by r/w# low having been registered into the device at adv/ld# low. a read cycle is defined by r/w# high with adv/ld# low. both cases must meet setup and hold times. ac electrical characteristics (notes 6, 8, 9) (0 c t a +70 c; v dd , v dd q = +3.3v 0.165v) -7.5 -10 description symbol min max min max units notes clock clock cycle time t khkh 7.5 10 ns clock frequency f kf 133 100 mhz clock high time t khkl 2.2 3.5 ns 1 clock low time t klkh 2.2 3.5 ns 1 output times clock to output valid t khqv 4.2 5.0 ns clock to output invalid t khqx 1.5 1.5 ns 2 clock to output in low-z t khqx1 1.5 1.5 ns 2, 3, 4, 5 clock to output in high-z t khqz 1.5 3.5 1.5 3.5 ns 2, 3, 4, 5 oe# to output valid t glqv 4.2 5.0 ns 6 oe# to output in low-z t glqx 0 0 ns 2, 3, 4, 5 oe# to output in high-z t ghqz 4.2 5.0 ns 2, 3, 4, 5 setup times address t avkh 2.0 2.0 ns 7 clock enable (cke#) t evkh 2.0 2.0 ns 7 control signals t cvkh 2.0 2.0 ns 7 data-in t dvkh 2.0 2.0 ns 7 hold times address t khax 0.5 0.5 ns 7 clock enable (cke#) t khex 0.5 0.5 ns 7 control signals t khcx 0.5 0.5 ns 7 data-in t khdx 0.5 0.5 ns 7
17 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram ac test conditions input pulse levels ................................... v ss to 3.0v input rise and fall times .................................. 1.0ns input timing reference levels .......................... 1.5v output reference levels ................................... 1.5v output load ............................. see figures 1 and 2 q 50 v = 1.5v z = 50 o t figure 1 q 351 317 5pf +3.3v figure 2 load derating curves the micron 128k x 18, 64k x 32, and 64k x 36 zbt sram timing is dependent upon the capacitive loading on the outputs. consult the factory for copies of i/o current versus voltage curves. output load equivalents
18 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram snooze mode snooze mode is a low-current, ?power-down? mode in which the device is deselected and current is reduced to i sb 2 z . the duration of snooze mode is dictated by the length of time the zz pin is in a high state. after the device enters snooze mode, all inputs except zz become disabled and all outputs go to high-z. the zz pin is an asynchronous, active high input that causes the device to enter snooze mode. when the zz pin becomes a logic high, i sb 2 z is guaranteed after the time t zzi is met. any read or write opera- tion pending when the device enters snooze mode is not guaranteed to complete successfully. therefore, snooze mode must not be initiated until valid pend- ing operations are completed. similarly, when exiting snooze mode during t rzz, only a deselect or read cycle should be given. snooze mode electrical characteristics description conditions symbol min max units notes current during snooze mode zz v ih i sb 2z 10 ma zz active to input ignored t zz 0 2( t khkh) ns 1 zz inactive to input sampled t rzz 0 2( t khkh) ns 1 zz active to snooze current t zzi 2( t khkh) ns 1 zz inactive to exit snooze current t rzzi 0 ns 1 snooze mode waveform t zz i supply clk zz t rzz all inputs (except zz) don ? t care i isb2z t zzi t rzzi outputs (q) high-z deselect or read only note: 1. this parameter is sampled.
19 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram note: 1. for this waveform, zz is tied low. 2. burst sequence order is determined by mode (0 = linear, 1 = interleaved). burst operations are optional. 3. ce# represents three signals. when ce# = 0, it represents ce# = 0, ce2# = 0, ce2 = 1. 4. data coherency is provided for all possible operations. if a read is initiated, the most current data is used. the most recent data may be from the input data register. read/write timing write d(a1) 123 456789 clk t khkh t klkh t khkl 10 ce# t khcx t cvkh r/w# cke# t khex t evkh bwx# adv/ld# t khax t avkh address a1 a2 a3 a4 a5 a6 a7 t khdx t dvkh dq command t khqx1 d(a1) d(a2) d(a5) q(a4) q(a3) d(a2+1) t khqx t khqz t khqv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe# t glqv t glqx t ghqz t khqx don ? t care undefined q(a6) q(a4+1) -7.5 -10 symbol min max min max units t ghqz 4.2 5.0 ns t avkh 2.0 2.0 ns t evkh 2.0 2.0 ns t cvkh 2.0 2.0 ns t dvkh 2.0 2.0 ns t khax 0.5 0.5 ns t khex 0.5 0.5 ns t khcx 0.5 0.5 ns t khdx 0.5 0.5 ns read/write timing parameters -7.5 -10 symbol min max min max units t khkh 7.5 10 ns f kf 133 100 mhz t khkl 2.2 3.5 ns t klkh 2.2 3.5 ns t khqv 4.2 5.0 ns t khqx 1.5 1.5 ns t khqx1 1.5 1.5 ns t khqz 1.5 3.5 1.5 3.5 ns t glqv 4.2 5.0 ns t glqx 0 0 ns
20 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram nop, stall, and deselect cycles read q(a3) 456 78910 clk ce# r/w# cke# bwx# adv/ld# address a3 a4 a5 d(a4) dq command a1 q(a5) write d(a4) stall write d(a1) 123 read q(a2) stall nop read q(a5) deselect continue deselect don ? t care undefined t khqz t khqx a2 d(a1) q(a2) q(a3) note: 1. the ignore clock edge or stall cycle (clock 3) illustrates cke# being used to create a ? pause. ? a write is not performed during this cycle. 2. for this waveform, zz and oe# are tied low. 3. ce# represents three signals. when ce# = 0, it represents ce# = 0, ce2# = 0, ce2 = 1. 4. data coherency is provided for all possible operations. if a read is initiated, the most current data is used. the most recent data may be from the input data register. nop, stall and deselect timing parameters -7.5 -10 symbol min max min max units t khqx 1.5 1.5 ns t khqz 1.5 3.5 1.5 3.5 ns
21 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram 165-pin fbga note: 1. all dimensions in millimeters max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 10.00 14.00 15.00 0.10 1.00 (typ) 1.00 (typ) 5.00 0.05 13.00 0.10 pin a1 id pin a1 id ball a1 mold compound: epoxy novolac substrate: plastic laminate 6.50 0.05 7.00 0.05 7.50 0.05 1.20 max solder ball material: eutectic 63% sn, 37% pb solder ball pad: ? .33mm seating plane 0.85 0.075 0.10 a a 165x ? 0.45 ball a11
22 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram 100-pin plastic tqfp (jedec lqfp) 14.00 0.10 20.10 0.10 0.62 22.10 +0.10 -0.15 16.00 +0.20 -0.05 pin #1 id 0.65 1.50 0.10 0.25 0.60 0.15 1.40 0.05 0.32 +0.06 -0.10 0.15 +0.03 -0.02 0.10 +0.10 -0.05 detail a detail a 1.00 (typ) gage plane 0.10 note: 1. all dimensions in millimeters max or typical here noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micronsemi.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc. zbt and zero bus turnaround are trademarks of integrated device technology, inc., and the architecture is supported by micron technology, inc., and motorola inc.
23 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l128l18p1_2.p65 ? rev. 8/00 ?2000, micron technology, inc. 2mb: 128k x 18, 64k x 32/36 3.3v i/o, pipelined zbt sram revision history removed fbga part marking guide, rev 8/00, final ........................................................................ august/22/00 changed fbga capacitance values, rev 8/00, final ............................................................................. au gust/7/00 c i ; typ 2.5pf from 4pf; max. 3.5pf from 5pf c o ; typ 4pf from 6pf; max. 5pf from 7pf c ck ; typ 2.5pf from 5pf; max. 3.5pf from 6pf removed it references, rev 7/00, final ......................................................................................... ............ july/10/00 added fbga part marking guide added revision history to datasheet removed it from part number example, rev 6/00, final ....................................................................... june /21/00 added # of datalines to the databus in x32/36 block diagram changed tkqlz from 4.0ns min to 1.5ns min added note - ?preliminary package data? to fbga capacitance and thermal resistance tables changed heading on mechanical drawing from bga to fbga added 165-pin fbga package, rev 3/00, final .................................................................................... ... may/23/00 added preliminary package data to diagram

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